// Copyright (C) 1953-2022 NUDT
// Verilog module name - command_parse_and_encapsulate_cc 
// Version: V3.4.0.20220226
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module command_parse_and_encapsulate_cc
(
        i_clk  ,
        i_rst_n,

        i_wr,
        iv_wdata,
        iv_addr,    
        i_rd,
       
        o_wr, 
        ov_rdata,
        ov_raddr,
        
        ov_cycle_length, 
        ov_base_time,
        o_base_time_wr,
        o_cc_cfg,
        o_cc_err		
);
// I/O
// i_clk & rst
input                  i_clk       ;
input                  i_rst_n     ;

input                  i_wr    ;
input      [31:0]      iv_wdata;
input      [18:0]      iv_addr ;      
input                  i_rd    ;
output reg             o_wr    ; 
output reg [31:0]      ov_rdata;  
output reg [18:0]      ov_raddr;

output reg [31:0]      ov_cycle_length ; 
output reg [79:0]      ov_base_time    ;
output reg             o_base_time_wr  ;
output reg             o_cc_cfg        ;
output reg             o_cc_err        ;
//***************************************************
//               command parse
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin       
        o_wr              <= 1'b0 ;
        ov_rdata          <= 32'b0;
        ov_raddr          <= 19'b0;
        
        ov_cycle_length       <= 32'd0;  
		ov_base_time          <= 80'd0; 
        o_base_time_wr       <= 1'b0;
        o_cc_cfg              <= 1'b0;
        o_cc_err              <= 1'b0;
    end
    else begin
        if(i_wr)begin
            o_wr          <= 1'b0;
            ov_rdata      <= 32'b0;
            ov_raddr      <= 19'b0;
            if(iv_addr == 19'd3)begin
                ov_cycle_length      <= iv_wdata;
            end
            else if (iv_addr == 19'd2)begin		
                ov_base_time[31:0]  <=	iv_wdata;
                o_base_time_wr      <= 1'b1;
            end	            
            else if (iv_addr == 19'd1)begin		
                ov_base_time[63:32] <=	iv_wdata;
                o_base_time_wr      <= 1'b0;
            end				
            else if (iv_addr == 19'd0)begin		
                ov_base_time[79:64] <=	iv_wdata[15:0];
                o_base_time_wr      <= 1'b0;
            end 
            else if (iv_addr == 19'd4)begin		
                o_cc_cfg            <=	iv_wdata[0];
            end
            else if (iv_addr == 19'd5)begin		
                o_cc_err            <=	iv_wdata[0];
            end   			
            else begin
                ov_cycle_length              <= ov_cycle_length; 
				ov_base_time                 <= ov_base_time;
                o_base_time_wr               <= 1'b0;
                o_cc_cfg                     <= o_cc_cfg;
                o_cc_err                     <= o_cc_err;
            end
        end      
        else if(i_rd)begin
            if(iv_addr == 19'd3)begin
                o_wr          <= 1'b1;
                ov_rdata      <= ov_cycle_length;
                ov_raddr      <= iv_addr;         
            end
			else if(iv_addr == 19'd2)begin
                o_wr          <= 1'b1;
                ov_rdata      <= ov_base_time[31:0];
                ov_raddr      <= iv_addr;
			end
			else if(iv_addr == 19'd1)begin
                o_wr          <= 1'b1;
                ov_rdata      <= ov_base_time[63:32];
                ov_raddr      <= iv_addr;
			end
			else if(iv_addr == 19'd0)begin
                o_wr          <= 1'b1;
                ov_rdata      <= {16'b0,ov_base_time[79:64]};
                ov_raddr      <= iv_addr;
			end            
			else if(iv_addr == 19'd4)begin
                o_wr          <= 1'b1;
                ov_rdata      <= {31'b0,o_cc_cfg};
                ov_raddr      <= iv_addr;
			end
			else if(iv_addr == 19'd5)begin
                o_wr          <= 1'b1;
                ov_rdata      <= {31'b0,o_cc_err};
                ov_raddr      <= iv_addr;
			end             
            else begin
                o_wr          <= 1'b1;
                ov_rdata      <= 32'hffffffff;
                ov_raddr      <= iv_addr ;
            end            
        end
        else begin
            ov_cycle_length             <= ov_cycle_length; 
            ov_base_time                <= ov_base_time;
            o_base_time_wr              <= 1'b0;
            o_cc_cfg                    <= o_cc_cfg;
            o_cc_err                    <= o_cc_err;            
            o_wr                     <= 1'b0;
            ov_rdata                 <= 32'b0;
            ov_raddr                 <= 19'b0;      
        end
    end
end    
endmodule
    
